1. Field of the Invention
The present invention relates to a decoder circuit, more particularly, to an output portion or a buffer portion of a dynamic type decoder circuit used for selecting a memory cell of a memory device.
2. Description of the Related Art
In the prior art, a decoder circuit is used for decoding an input signal and for selecting and outputting an appropriate signal one of, a plurality of signal conductors. A decoder circuit is used for various purposes, but in the example given below, the decoder circuit is used for selecting a memory cell of a memory such as a ROM (Read Only Memory) or PLA (Programmable Logic Array), and the like.
For example, a conventional decoder circuit comprises a decoder portion, a buffer portion, and a control portion. The decoder portion includes input signal conductors and output signal conductors, the input signal conductors being complementary signal conductors and the output signal conductors being provided so as to cross the input signal conductors. A cell transistor is provided for each crossed portion of the input signal conductors and the output signal conductors, and one of the output signal conductors is selected in accordance with logic decoding of the contents information content of the input signals. Output portions of the output signal conductors are provided, for example, with NAND circuits, and the input terminal of each of the NAND circuits is connected to a corresponding one of the output signal conductors and the other input terminal thereof is supplied with a timing signal. This timing signal is input to the aforesaid other input terminals of all the NAND circuits after changing the potential of the output signal conductors, except for the aforesaid one, selected output signal conductor, to a low level. Namely, the timing signal is used to avoid a selection error, and this timing signal is output from a control portion in the decoder circuit. The control portion comprises, for example, an inverter having an input supplied with the potential of a dummy signal conductor wired in the same manner as the output signal conductors, a NAND circuit, and an inverter.
The above conventional decoder circuit has problems in that the timing signal should be applied to the NAND circuit, and the word lines should be driven by the timing signal through the NAND circuit in the output portions of the output signal conductors. Namely, the timing signal should be generated after all unselected output signal conductors have been fully discharged. Therefore, the output timing of the timing signal must include a time margin, taking into consideration the discharge time required for fully discharging an electrical charge in each of the output signal conductors, whereby the drive timing of the word line corresponding to the selected output signal conductor is delayed and thus hinders high speed operation of the decoder circuit. Further, the NAND circuits in the output portions of the output signal conductors and the control portions must be provided, and thus the construction of the decoder circuit becomes complicated.